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DS1371 2-Wire, 32-Bit Binary Counter Watchdog Clock
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General Description
The DS1371 is a 32-bit binary counter that is designed to continuously count time in seconds. An additional counter that can generate a periodic alarm or serve as a watchdog timer is also provided. If enabled as a watchdog timer, the watchdog strobe input pin provides a hardware reset of the counter. If disabled, this counter can be used as 3 Bytes of generalpurpose RAM. A configurable output can be used as an interrupt or provide a square wave at one of four selectable frequencies. The device is programmed serially through a 2-wire bidirectional bus.
Features
32-Bit Binary Counter 24-Bit Binary Counter Provides Periodic Alarm, Watchdog Timer, or RAM Strobe Input to Reset Watchdog Timer Single Output Configurable as Interrupt or Square Wave 2-Wire Serial Interface Low-Voltage Operation Operating Temperature Range: -40C to +85C Available in 8-Pin mSOP
Ordering Information
PART DS1371U TEMP RANGE -40C to +85C PINPACKAGE 8 SOP TOP MARK DS1371
Applications
Servers Point-of-Sale Equipment Portable Instruments Elapsed Time Measurements
Pin Configuration
TOP VIEW
Typical Operating Circuit
X1 X2 WDS GND
1 2 3 4
8 7 6 5
VCC SQW/INT SCL SDA
DS1371
SOP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 051203
DS1371
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Pin Relative to Ground Voltage Range on SDA, SCL, and WDS Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature -0.3V to +6.0V -0.3V to VCC +0.5V -40C to +85C -55C to +125C See IPC/JEDEC J-STD-020A
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C)
PARAMETER Supply Voltage (Note 1) Input Logic 1 (Notes 2, 3) Input Logic 0 (Notes 2, 3)
SYMBOL VCC VIH VIL
MIN 1.7 0.7 VCC -0.3
TYP 3.3
MAX 5.5 VCC + 0.3 0.3VCC
UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = 1.7V to 5.5V, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER Supply Voltage (Note 1) Oscillator Operating Voltage Range (Note 1) Input Leakage I/O Leakage SDA Logic 0 Output (Note 1)
SYMBOL VCC VOSC ILI ILO IOLSDA
CONDITIONS
MIN 1.7 1.3
TYP
MAX 5.5 5.5 1 1 3 3.0 3.0 250
UNITS V V mA mA mA mA mA mA nA nA nA
(Note 2) (Note 3) VCC > 2V; VOL = 0.4V VCC < 2V; VOL = 0.2VCC VCC > 2V; VOL = 0.4V 1.7V < VCC < 2V; VOL = 0.2VCC 1.3V < VCC < 1.7V; VOL = 0.2VCC (Note 5) (Notes 6, 7) (Notes 6, 7) (Note 6) 100
SQW/INT Logic 0 Output (Note 1) Active Supply Current Timekeeping Current (Oscillator Enabled, INTCN = 1) Timekeeping Current (Oscillator Enabled, INTCN = 0) Data Retention Current (Oscillator Disabled)
IOLSQW
ICCA IOSC0 IOSC1 IDDR
150 800 1300 50
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AC ELECTRICAL CHARACTERISTICS
(VCC = 1.7V to 5.5V, TA = -40C to +85C, unless otherwise noted.) (Note 8)
PARAMETER SCL Clock Frequency (Note 9) Bus Free Time Between STOP and START Conditions Hold Time (repeated) START Condition (Note 10) Low Period of SCL Clock High Period of SCL Clock Data Hold Time (Notes 11, 12) Data Setup Time (Note 13) Start Setup Time Rise Time of Both SDA and SCL Signals (Note 9) Fall Time of Both SDA and SCL Signals (Note 9) Setup Time for STOP Condition Capacitive Load for Each Bus Line (Note 7) Pulse Width of Spikes that Must be Suppressed by the Input Filter (Note 14) Watchdog Strobe (WDS) Pulse Width Oscillator Stop Flag (OSF) Delay (Note 8)
SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR
CONDITIONS Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode
tF Standard mode tSU:STO CB TSP tWDS tOSF Fast mode Fast mode Standard mode
MIN 100 0 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0 0 100 250 0.6 4.7 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 4.7
TYP
MAX 400 100
UNITS kHz ms ms ms ms
0.9 0.9
ms ns ms
300 ns 1000 300 ns 300 ms 400 30 pF ns ns ms
100 100
Note 1: All voltages are referenced to ground. Note 2: SCL and WDS only. Note 3: SDA and SQW/INT. Note 4: Limits at -40C are guaranteed by design and not production tested. Note 5: ICCA--SCL clocking at max frequency = 400kHz. WDS inactive. Note 6: Specified with WDS input and 2-wire bus inactive, SCL = SDA = VCC. Note 7: Measured with a 32.768kHz crystal attached to the X1 and X2 pins. Note 8: The parameter tOSF is the period of time the oscillator must be stopped in order for the OSF flag to be set over the voltage range of 1.3V VCC VCCMAX. Note 9: A fast mode device can be used in a standard mode system, but the requirement tSU:DAT to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 10: After this period, the first clock pulse is generated. Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Note 12: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 13: CB--total capacitance of one bus line in pF. Note 14: This parameter is not production tested.
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DS1371
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
IOSCO vs. VCC SQUARE-WAVE OFF
DS1371 toc01
IOSC1 vs. VCC SQUARE-WAVE ON
900 850 SUPPLY CURRENT (nA) 800 750 700 650 600 550 500 450 400
DS1371 toc02
600 550 SUPPLY CURRENT (nA) 500 450 400 350 300 1.5 2.0 2.5 3.0 3.5 VCC (V) 4.0 4.5 5.0
950
5.5
1.5
2.0
2.5
3.0
3.5 VCC (V)
4.0
4.5
5.0
5.5
IOSC0 vs. TEMPERATURE VCC = 3.3V
DS1371 toc03
ICCA vs. VCC SQUARE-WAVE ON
75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 -40 -20 0 20 40 60 80 TEMPERATURE ( C)
DS1371 toc04
750 700 SUPPLY CURRENT (nA) 650
600 550 500 -40 -20 0 20 40 60 80 TEMPERATURE ( C)
IOSC0 vs. WDS FREQUENCY
DS1371 toc05
SUPPLY CURRENT (A)
OSCILLATOR FREQUENCY vs. VCC
32767.76
DS1371 toc06
35 30 SUPPLY CURRENT (A) 25 20 15 10 5 0 0 200 400 600 800
FREQUENCY (Hz) 1000
32767.71
32767.66
32767.61
3.767.56 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC (V)
WDS FREQUENCY (kHz)
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DS1371
Figure 1. Timing Diagram
Figure 2. Functional Diagram
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PIN DESCRIPTION
PIN NAME FUNCTION These signals are connections for a standard 32.768kHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6pF. 1, 2 X1, X2 For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. The DS1371 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Watchdog Input. A positive edge-triggered hardware interrupt input that restarts the watchdog counter when this signal transitions from a low to a high. While WDS remains at a static low or high, the watchdog counter continues to decrement. Ground 2-Wire Serial Data. Input/output for 2-wire data. 2-Wire Serial Clock. Input for 2-wire clock. Square-Wave/Interrupt Output. This pin is used to output the programmable squarewave or alarm interrupt signal. It is open drain and requires an external pullup resistor. Supply Voltage Terminal
3 4 5 6 7 8
WDS GND SDA SCL SQW/INT VCC
Detailed Description
The DS1371 is a real-time clock (RTC) with a 2-wire serial interface that provides elapsed seconds from a user-defined starting point in a 32-bit counter (Figure 2). A 24-bit counter can be configured as either a watchdog counter or as an alarm counter. An on-chip oscillator circuit uses a customer-supplied 32.768kHz crystal to keep time.
Oscillator Circuit
The DS1371 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal; Figure 3 shows a functional schematic of the oscillator circuit. Using a crystal with the specified characteristics, the startup time is usually less than one second.
Clock Accuracy
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 4 shows a typical PC board layout for isolation of the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information.
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DS1371
Table 1. Crystal Specifications*
PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL FO ESR CL MIN TYP 32.768 45 6 MAX UNITS kHz k pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
Figure 3. Oscillator Circuit Showing Internal Bias Network
Figure 4. Layout Example
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DS1371
Address Map
Table 2 shows the address map for the registers of the DS1371. During a multibyte access, when the address pointer reaches the end of the register space (08h), it wraps around to location 00h. On a 2-wire START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to reread the registers in case of an update of the main registers during a read.
Table 2. Address Map
ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H EOSC OSF WACE 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION Time-of-Day Counter Time-of-Day Counter Time-of-Day Counter Time-of-Day Counter Watchdog/Alarm Counter Watchdog/Alarm Counter Watchdog/Alarm Counter RS2 0 RS1 0 AIE AF Control Status TOD COUNTER BYTE 0 TOD COUNTER BYTE 1 TOD COUNTER BYTE 2 TOD COUNTER BYTE 3 WD/ALM COUNTER BYTE 0 WD/ALM COUNTER BYTE 1 WD/ALM COUNTER BYTE 2 WD/ ALM 0 0 0 INTCN 0
Note: Unless otherwise specified, the state of the registers are not defined when power is first applied.
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DS1371
Time-of-Day Counter
The time-of-day counter is a 32-bit up counter. The contents can be read or written by accessing the address range 00h-03h. When the counter is read, the current time of day is latched into a register, which is output on the serial data line while the counter continues to increment. Writing to the counter resets the countdown chain for the time-of-day counter (Figure 2). The watchdog countdown chain is unaffected. If the square-wave output is enabled and is set to 1Hz, the output resets when the countdown chain is reset. Because the other square-wave frequencies are derived before the section of the countdown chain that is reset, the other frequencies are unaffected by a write to the time-of-day counter.
Watchdog/Alarm Counter
The watchdog/alarm counter is a 24-bit down counter. The contents can be read or written by accessing the address range 04h-06h. When this counter is written, both the counter and a seed register are loaded with the written value. The countdown chain for the watchdog counter is reset when the counter is written. The time-of-day countdown chain is unaffected. When the counter is to be reloaded, it uses the value in the seed register. In alarm mode, when the counter is read, the current counter value is latched into a register, which is output on the serial data line while the counter continues to decrement. In watchdog mode, reading any of the watchdog registers reloads the seed value. If the counter is not needed, it can be disabled and used as a 24-bit cache of general-purpose RAM by setting the WACE bit in the control register to logic 0. If all 24 bits of the watchdog/alarm counter are written to a 0 when WACE = 1, the counter is disabled and the AF bit is not set. When the WD/ALM bit in the control register is set to a logic 0, the WD/ALM counter decrements every second, until it reaches 0. At this point, the AF bit in the status register is set, the counter is reloaded, and restarted. When the WD/ALM bit is set to a logic 1, the WD/ALM counter decrements every 1/4096 of a second (approximately every 244s) until it reaches 0, sets the AF bit in the status register, and stops. If AIE = 1 and INTCN = 1, the SQW/INT pin pulses low for 250ms. The pulse cannot be truncated by writing either AF or AIE to a 0 during the low time of the SQW/INT pin. At the end of the 250ms pulse, the AF bit is cleared to a 0 and the SQW/INT pin becomes high impedance. The WD/ALM counter can be reloaded and restarted before the counter reaches 0 by: 1) Reading or writing any of the WD/ALM counter registers (WDS must be low). 2) A low-to-high transition on the WDS pin.
Note: WDS must be low when configuring the watchdog.
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DS1371
Special Purpose Registers
The DS1371 has two additional registers (07h-08h) that control the WD/ALM counter, square-wave output, and interrupts. Control Register (07h)
Bit # Name Default 7 EOSC 0 6 WACE 0 5 WD/ALM 0 4 0 0 3 INTCN 0 2 RS2 1 1 RS1 1 0 AIE 0
Bit 7/Enable Oscillator (EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is stopped. When this bit is set to a logic 1, the oscillator is stopped and the DS1371 is placed into a low-power standby mode (IDDR). This bit is clear (logic 0) when power is first applied. Bit 6/WD/ALM Counter Enable (WACE). When set to logic 1, the WD/ALM counter is enabled. When set to logic 0, the WD/ALM counter is disabled, and the 24-bits can be used as general-purpose RAM. This bit is clear (logic 0) when power is first applied. Bit 5/WD/ALM Counter Select (WD/ALM). When set to logic 0, the counter decrements every second until it reaches 0 and is then reloaded and restarted. When set to logic 1, the WD/ALM counter decrements every 1/4096 of a second (approximately every 244s) until it reaches 0, sets the AF bit in the status register, and stops. If any of the WD/ALM counter registers are read or written, or a rising edge on the WDS pin occurs before the counter reaches 0, the counter is reloaded and restarted. This bit is clear (logic 0) when power is first applied. Bit 3/Interrupt Control (INTCN). This bit controls the SQW/INT signal. When the INTCN bit is set to logic 0, a square wave is output on the SQW/INT pin whose frequency is defined by bits RS2 and RS1. The oscillator must also be enabled for the square wave to be output. When the INTCN bit is set to logic 1, then this permits the alarm flag bit in the status register to assert SQW/INT (provided that the alarm is also enabled). The alarm flag is always set, regardless of the state of the INTCN bit. The INTCN bit is set to logic 0 when power is first applied. Bits 2, 1/Rate Select 1 and 2 (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. Table 3 shows the square-wave frequencies that can be selected with the RS bits. These bits are both set (logic 1) when power is first applied. Bit 0/Alarm Interrupt Enable (AIE). When set to logic 1, this bit permits the AF bit in the status register to assert SQW/INT (when INTCN = 1). When set to logic 0 or INTCN is set to logic 0, the AF bit does not initiate the SQW/INT signal. If the WD/ALM bit is set to a logic 1 and the AF flag is set, writing AIE to a 0 does not truncate the 250ms pulse on the SQW/INT pin. The AIE bit is at logic 0 when power is first applied.
Table 3. Square-Wave Output Frequency
RS2 0 0 1 1 RS1 0 1 0 1 SQUARE-WAVE OUTPUT FREQUENCY 1Hz 4.096kHz 8.192kHz 32.768kHz
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DS1371
Status Register (08h)
Bit # Name Default 7 OSF 1 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 AF --
Bit 7/Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period and can be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: * The first time power is applied. * The voltage present on VCC is insufficient to support oscillation. * The EOSC bit is turned off. * External influences on the crystal (e.g., noise, leakage, etc.) * This bit remains at logic 1 until written to logic 0. Bit 0/Alarm Flag (AF). A logic 1 in the AF bit indicates that the WD/ALM counter reached 0. If INTCN is set to a 1, and WD/ALM is set to 0 and AIE is set to 1, the SQW/INT pin goes low and stays low until AF is cleared. AF is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write logic 1 leaves the value unchanged. If INTCN and WD/ALM are set to 1 and the AIE is set to 1, the SQW/INT pin pulses low for 250ms when the WD/ALM counter reaches 0 and sets AF = 1. At the completion of the 250ms pulse, the DS1371 clears the AF bit to a 0. If the 250ms pulse is active, writing AF to a 0 does not truncate the pulse.
2-Wire Serial Interface
The DS1371 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a "master." The devices that are controlled by the master are "slaves." The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1371 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (Figure 5): * * Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high are interpreted as control signals.
Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line from high to low, while the clock line is high, defines a START condition. Stop data transfer: A change in the state of the data line from low to high, while the clock line is high, defines a STOP condition.
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DS1371
Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and the STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the 2-wire bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
Figure 5. 2-Wire Data Transfer Overview
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DS1371
Figures 6 and 7 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1371 can operate in the following two modes: Slave receiver mode (DS1371 write mode). Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit DS1371 address, which is 1101000, followed by the direction bit (R/W), which for a write is a 0. After receiving and decoding the slave address byte the DS1371 outputs an acknowledge on SDA. After the DS1371 acknowledges the slave address + write bit, the master transmits a word address to the DS1371. This sets the register pointer on the DS1371, with the DS1371 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the DS1371 acknowledging each byte received. The register pointer increments after each byte is transferred. The master generates a STOP condition to terminate the data write. Slave transmitter mode (DS1371 read mode). The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1371 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit DS1371 address, which is 1101000, followed by the direction bit (R/W), which for a read is a 1. After receiving and decoding the slave address byte, the DS1371 outputs an acknowledge on SDA. The DS1371 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The DS1371 must receive a "not acknowledge" to end a read.
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DS1371
Figure 6. 2-Wire Write Protocol
Figure 7. 2-Wire Read Protocol
Chip Information
TRANSISTOR COUNT: 11,036 PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND
Thermal Information
Theta-JA: 221C/W Theta-JC: 39C/W
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2003 Maxim Integrated Products * Printed USA
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